In advanced semiconductor chips operating at frequencies above 1 GHz range, signal propagation delay between various devices or components in the semiconductor chip accounts for a significant fraction of overall chip operation speed. The signal propagation delay in an interconnect structure is dependent on an RC product of the interconnect structure, where R denotes the resistance of the interconnect wires and C denotes the interconnect capacitance, or the overall capacitance of the interconnect structure in which the interconnect wires are embedded. The continuous shrinking in dimensions of electronic devices utilized in ultra-large scale integration (ULSI) circuits in recent years has resulted in increase in the resistance of the back-end of the line (BEOL) metallization as well as an increase in the intralayer and interlayer dielectric capacitance. Thus, reduction of the resistance and the capacitance of the BEOL metallization is paramount in enhancing performance of the advanced semiconductor chips.
Use of copper instead of aluminum as the interconnect wiring material for the BEOL metallization has allowed reduction of the resistance contribution to the RC product. Current focus in microelectronics industry is on reducing the interconnect capacitance by employing low dielectric constant (low k) dielectric materials in the interconnect structure of the advanced semiconductor chips, which typically contain a multilayered interconnect structure. While attempts to integrate various materials having a low dielectric constant, commonly referred to as “low-k materials” in the art, have produced some successful results in the art for materials having a dielectric constant of about 2.8 or greater, integration of ultra low dielectric constant (ultra low-k) material into the BEOL metallization faces several significant challenges.
Typical ultra low-k materials include various types of organosilicate glass (OSG), which contains Si, C, O, and H, and is oftentimes referred to as a SiCOH dielectric material. Efforts to integrate ultra low-k materials into BEOL interconnect wiring structures demonstrated that the ultra low-k materials have a tendency to crack, especially at high humidity environments. The driving force for cracking is inversely proportional to the Young's modulus E, of the ultra low-k dielectric, and proportional to the square of biaxial stress applied to the ultra low-k dielectric material.
For small values of an applied stress tensor during elastic deformation, the magnitude of the strain tensor of an elastic solid is linearly proportional to the magnitude of the stress tensor applied on it. The ratio of the stress to strain in the linear elastic region is known as Young's modulus tensor, E, which is also known as the elastic modulus tensor. The stress tensor, σ, the Young's modulus tensor, E, and the strain tensor, ∈, satisfy the following relationship: σ=E·∈. In general, the Young's modulus tensor, E, is a fourth order tensor with 81 components, which can be reduced to 21 independent components for any elastic material by considering symmetry and constraints on strain energy. If the material is isotropic, the 81 components of Young's modulus tensor, E, may further be reduced to the diagonal components that have the same value, E, and some non-diagonal components with the value of the ratio of Young's modulus to Poisson's ratio ν, i.e., E/ν. Young's modulus, E, as the diagonal components of the fourth order Young's modulus tensor is commonly referred to, is a measure of the stiffness of a material, i.e., the higher the Young's modulus of a material, the stiffer it is, and the less strain it exhibits for a given stress.
Increasing Young's modulus E and reducing the stress are very important for minimizing the cracking issue in low k dielectric layer. While stress is an external parameter generated as a function of geometry during processing, Young's modulus E is a material property that may be manipulated by subjecting the ultra low-k material to a suitable treatment. By increasing Young's modulus E of the ultra low-k material, the strain of the ultra low-k material may be lowered for a given external stress.
One way to increase Young's modulus E, i.e., the stiffness of a ultra low-k dielectric material, is to expose the ultra low-k dielectric material to a beam of energetic electrons, i.e., an electron beam (e-beam) such as a flood electron beam. Such treatments are called electron beam curing. Electron beam curing usually results in a significant increase of Young's modulus E and hardness in an ultra low-k dielectric material, which can then be integrated into BEOL metallization structures with a reduced risk of cracking. Unfortunately, an electron beam treatment has undesirable side effects on front-end of the line (FEOL) devices, e.g., field effect transistors (FETs). Such effects include reduced break down voltage characteristics, large threshold voltage shifts, and other adverse effects attributed to charging of the substrate and various films on it, due to the electron beam.
In view of the above, there exists a need for a method of electron beam curing of ultra low-k dielectric material, while preventing any damages or side effects on semiconductor devices located in the same substrate.
Further, there exists a need for a method of electron beam curing of ultra low-k dielectric material without inducing charging on the substrate containing the ultra low-k dielectric material and various films and structures fabricated on it.